1. Field of the Invention
The present invention relates to a driver circuit that outputs a drive signal, and particularly to a liquid crystal display driving semiconductor device for driving a liquid crystal.
2. Description of the Related Art
TFT(Thin-Film Transistor) active-matrix liquid crystal display devices that realize display by incorporating address TFTs in matrix form within liquid crystal panel are currently the mainstream in matrix liquid crystal display devices. Source drivers that send image signals and gate drivers that send scanning signals for effecting line sequential scanning are used to drive TFT active-matrix liquid crystal display devices.
A gate driver is a device that impresses voltage to the gate electrodes of TFTs in accordance with timing signals for row electrode scanning that are generated from image signals in a signal conversion circuit. Assuming that one horizontal interval (scanning interval) is H, a gate driver impresses for every row a scanning signal having a pulse width of H to the scanning electrodes, and sets TFTs on the panel to a sequential ON state for every row. Here, it is assumed that one horizontal interval (scanning interval) H is equal to T/N if T is one frame (all scanning intervals) of row electrodes and N is the number of row electrodes. Image signals are converted by the signal conversion circuit and .gamma.-correction circuit to alternating-current driving signals that accord with the voltage-transmittance ratio characteristic of a liquid crystal and are impressed to liquid crystals by way of TFTS that have been turned ON by a source driver. Voltage suitable for the liquid crystals of all pixels can be impressed by repeating this operation for all row electrodes.
The time interval for repeating the above-described operation for all rows is one frame. However, one frame interval T must be a time interval in which a user cannot perceive line sequential scanning, and one horizontal interval H must be made longer than the time interval in which the voltage across the capacitance of the liquid crystal becomes the voltage impressed by the source driver.
Gray-level display in a TFT active-matrix liquid crystal display device is realized by varying the voltage impressed to the liquid crystal. The transmittance of light varies according to the voltage impressed to the liquid crystal due to the upper and lower polarizers and the electrical optical characteristics of a liquid crystal sandwiched between these polarizers. The brightness (tone) of light that is transmitted from the backlight behind a liquid crystal panel and through the liquid crystal panel is therefore determined by the voltage impressed to the liquid crystal.
Recent years have seen the development of color (multi-tone) and high-definition TFT active-matrix liquid crystal display devices.
In accordance with the voltage-transmittance characteristics of a liquid crystal, transmittance varies widely with slight changes in voltage if transmittance is at a medium level. To realize multi-tone displays, voltage must be impressed to the liquid crystal layer at high accuracy so that the liquid crystal has the desired transmittance.
The offset voltage of operational amplifiers used in the output of source drivers exhibits a spread of several mV even on the same chip. When displaying the same tone on a panel, the occurrence of any variation in the offset voltage of each operational amplifier within a source driver that impresses voltage to each pixel according to the voltage-transmittance characteristic of the liquid crystal will give rise to discrepancies in the transmittance of the liquid crystal because the voltage that is impressed varies between pixels to the extent of the offset voltage. In cases of a large number of tones, slight discrepancies in the transmittance of the liquid crystals are manifested as discrepancies in the tones of the display device, thereby degrading the quality of the display device. Multi-tone displays therefore require a degree of accuracy such that offset voltage can be ignored.
The circuit of a switched capacitor D/A(digital-to-analog) converter that is shown in FIG. 1 is made up of: V1 and V2 as analog input and reference voltage Vr; operational amplifier D1 having its positive input terminal connected to reference power supply voltage Vr; capacitor C1 provided with a capacitance of nC and capacitor C2 provided with a capacitance of (.alpha.-n)C, the two capacitors C1 and C2 being connected in parallel between the negative input terminal of operational amplifier D1 and power supplies V1 and V2, respectively; capacitor C3 provided with a capacitance of .alpha.C and connected between the negative input terminal and the output terminal of operational amplifier D1; switch SW1 provided between power supply V1 and the side of capacitor C1 that is not connected to operational amplifier D1; switches SW2 and SW3 connected in a series between V2 and the side of capacitor C1 that is not connected to operational amplifier D1; switch SW4 provided between the side of switch SW2 that is not connected to V2 and the positive input terminal of operational amplifier D1; switch SW8 provided between the negative input terminal and output terminal of operational amplifier D1 and in parallel with capacitor C3; and switch SW9 connected to the output terminal of operational amplifier D1 for cutting off the connection with an external load (not shown in the figure). In addition, capacitor C2 is connected to V2 by way of switch SW2.
Explanation is next presented regarding the operation of the circuit configured according to the description above.
Switch SW9 is first set in the OFF state to isolate this circuit from external load (not shown), such that the circuit is not subject to influence from the outside in the resetting operation.
Next, switches SW1 and SW2 are set to an OFF state, and switches SW3, SW4, and SW8 are each set to the ON state, whereupon operational amplifier D1 functions as a voltage follower and ideally, the potential at the negative input terminal of operational amplifier D1 becomes equal to the voltage Vr at the positive input terminal, thereby effecting resetting of the circuit.
After resetting has been completed, switches SW1 and SW2 are set to an ON state, switches SW3, SW4 and SW8 are set to an OFF state, and the output preparation operation Vout=2 Vr-V2-n (V1-V2)/.alpha. to the exterior, which is the output of the circuit, is carried out.
When switch SW9 is subsequently set to an ON state, the above-described output preparation Vout=2Vr-V2-n (V1-V2)/.alpha. is outputted to the exterior, and is applied to external load.
The operational amplifier is made to function as a voltage follower when resetting in the above-described device of the prior art, and carrying out a resetting operation in this way may easily bring about ringing in response to the light load in the circuit.
In the above-described prior-art circuit, there is an interval of 2-3 .mu.s from the start of the resetting operation until stabilization of the potential at the negative input terminal of the operational amplifier, as shown in FIG. 2.
With the development of larger sizes and higher definition in liquid crystal display devices in recent years, there has been a growing demand for a shorter time interval for driving the liquid crystal.
When a device that requires a time interval of 2-3 .mu.s for resetting is used in a large-scale or high-definition liquid crystal display device, the drive time for an element ends before the potential stabilizes, and the desired voltage therefore cannot be applied to the liquid crystal. This failure raises the concern that the resulting display will differ from the intended display.